1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a body contact of a silicon on insulator metal oxide semiconductor field effect transistor (hereinafter, referred to as xe2x80x9cSOI MOSFETxe2x80x9d).
2. Description of the Related Art
Body contacts are intended to prevent the floating body effect in a transistor. The floating body effect is a phenomenon in which the threshold voltage of the transistor varies because the body of the transistor does not have a certain fixed voltage value during operation. The floating body effect is particularly important in MOS analog techniques. A node having a predetermined direct current (DC) voltage is connected to the body of a transistor when designing MOS analog circuits in order to prevent the floating body effect. The low voltage source or the high voltage source of a chip is connected to the body of a transistor depending on the type (pxe2x88x92 type or nxe2x88x92 type) of the body in a digital circuit. Even in the case of SOI MOSFETs, bodies of transistors have predetermined voltages applied so that the body floating effect does not occur.
Hereinafter, the prior art will be described with reference to the attached drawings. Like reference numerals in the drawings denote the same features in the drawings.
FIG. 1 is a plan view of a SOI MOSFET having a body contact according to a conventional trench method. Referring to FIG. 1, the SOI MOSFET includes an external trench isolation ring 11, a body power supply ring 12 having a p+ (p plus) region, a partial trench isolation ring 13 isolated from a peripheral active region, an active region 14, e.g., a drain of a transistor, an active region 15, e.g., a source of the transistor, a gate 16 between the drain and the source, a contact window 17 contacting the power supply ring 12, and a peripheral active region 19.
FIG. 2 is a cross-sectional view of the SOI MOSFET shown in FIG. 1 taken along line Xxe2x80x94X. FIG. 2 shows a pxe2x88x92 type semiconductor substrate 20, a buried oxide layer 21 on the pxe2x88x92 type semiconductor substrate 20, pxe2x88x92 type bodies 14 and 15 on the buried oxide layer 21, a partial trench isolation ring 13 around the pxe2x88x92 type bodies 14 and 15, a p+ body power supply ring 12 next to the partial trench isolation ring 13, an external trench isolation ring 11 next to the p+ body power supply ring 12, a gate oxide layer 18 on the pxe2x88x92 bodies 14 and 15, a gate 16 on the gate oxide layer 18, and a peripheral active region 19.
FIG. 3 is a cross-sectional view of the SOI MOSFET shown in FIG. 1 taken along line Yxe2x80x94Y. FIG. 3 shows a pxe2x88x92 type semiconductor substrate 20, a buried oxide layer 21 on the pxe2x88x92 type semiconductor substrate 20, a drain 14 and a source 15 on the buried oxide layer 21, a gate 16 between the drain 14 and the source 15, a gate oxide layer 18 underneath the gate 16, a partial trench isolation ring 13 around the drain 14 and the source 15, a body power supply ring 12, which is next to the partial trench isolation ring 13, for supplying power to a body, i.e., a p+ region, an external trench isolation ring 11, and a pxe2x88x92 region 22 underneath the partial trench isolation ring 13.
Stray capacitance exists at contacts 100 and 110 between the p+ region, i.e., the body contact 12, and the pxe2x88x92 region, i.e., the bodies 14 and 15 of the transistor in the SOI MOSFET shown in FIGS. 1, 2, and 3. Stray capacitance can limit the performance of the transistor, especially, the operating speed and frequency of a circuit. It is not easy to form a metal interconnection line which needs a wide area in view of the layout when a voltage, e.g., ground voltage, must be applied to a body.
To solve the above problems, it is an object of the present invention to provide an SOI MOSFET that can reduce a floating body effect without stray capacitance at a contact and an additional metal interconnection line supplying power to the contact.
It is another object of the present invention to provide a method fabricating the same.
Accordingly, to achieve the above first object, there is provided a silicon-on-insulator metal oxide semiconductor field effect transistor (SOI MOSFET). The SOI MOSFET includes a semiconductor substrate, a buried oxide layer, a body, a gate oxide layer, a gate, and a body contact. The semiconductor substrate can be a semiconductor wafer. The buried oxide layer is an oxide layer which is formed on the semiconductor substrate. The body is an active region of a transistor which is formed on the buried oxide layer. The gate oxide layer is formed on the body, and the gate is formed on the gate oxide layer. The body contact supplies power to the body to prevent a floating body effect. The body contact is formed by forming a trench perforating an isolation region surrounding the body, the body, and the buried oxide layer and then filling the trench with a conductive material so that the body is electrically connected to the semiconductor substrate.
The conductive material can be formed of one of a metal layer, a tungsten layer, a silicon epitaxial layer and a combination of at least two of the above layers. The gate can be formed of metal or polysilicon
The SOI MOSFET further includes a region into which predetermined impurity ions are implanted and generated on the semiconductor substrate in contact with the lower portion of the body contact so that an ohmic contact is formed between the body contact and the semiconductor substrate.
In one embodiment, the trench narrows as the trench deepens. Alternatively, the trench narrows in a step-wise manner as the trench deepens. In accordance with the invention, there is also provided a method of fabricating a SOI MOSFET. In the method, a buried oxide layer is formed on a semiconductor substrate. A silicon body is formed on the buried oxide layer. The silicon body is defined as a channel region, a body contact, an isolation region, a field oxide layer region, a peripheral region, and the isolation region and the field oxide layer are etched. The isolation region is further etched until the buried oxide layer is exposed. Oxide layers are formed in the isolation region and the field oxide layer region. A gate oxide layer is formed on a predetermined region on the body and a gate is formed on the gate oxide layer. The semiconductor substrate is etched from an upper part toward a lower part so that the body and the buried oxide layer are perforated to form a trench. Predetermined impurity ions are implanted into a predetermined region of the semiconductor substrate to form an ohmic contact. The trench is filled with a conductive material.
In one embodiment, the predetermined region of the semiconductor substrate into which the impurity ions are implanted is the bottom of the trench.